Performance

Memory hierarchy

L1 ~1ns, L2 ~4ns, L3 ~12ns, RAM ~100ns, SSD ~100µs, network ~1ms.


In plain terms

Each level is ~10× slower than the last. Cache locality dominates algorithmic complexity for small n.

Origin

The L1/L2/L3/RAM/disk model goes back to Maurice Wilkes's "slave memory" idea (1965). Jeff Dean's "Latency numbers every programmer should know" (2009) made it standard tech-interview canon.

Where it shows up in production
  • CPU L1 vs RAM ~1ns vs ~100ns — a 100× gap. Cache-friendly algorithms beat cache-hostile ones easily at the same big-O.
  • NVMe SSD ~100μs random read — 1000× faster than spinning disk, still 1000× slower than RAM.
On Semicolony
Sources & further reading
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