Computer architecture, chapter by chapter
The 15 chapters follow the hardware from the bottom up: logic gates, then the processor, then memory, then devices, and finally what happens at power-on. Each chapter stands on its own, so if you came for one topic, start there and follow the links inside it.
For an overview, the main ideas, latency figures and reading list, see the computer architecture overview.
The processor
From transistors up to a core that runs several instructions per clock cycle.
- 01 Transistors, gates and the ALU
How transistors make logic gates, and how gates combine into a circuit that adds and compares numbers.
Try it: Build a CPU from NAND gates - 02 Clocks, latches and flip-flops
How a chip holds a value from one clock tick to the next, and why clock speeds stopped rising at around 5 GHz.
- 03 The instruction cycle
Fetch, decode, execute and write back, following one RISC-V instruction through the processor.
- 04 Pipelining
Overlapping instructions like an assembly line: the classic five stages, and why real cores use many more.
- 05 Branch prediction and speculation
How a CPU guesses which way a branch will go before it knows, what a wrong guess costs, and how Spectre abused the guessing.
- 06 Out-of-order execution
Running instructions as soon as their inputs are ready instead of in program order, using register renaming and a reorder buffer.
- 07 SIMD and vector instructions
One instruction working on many values at once (SSE, AVX, AVX-512, NEON and SVE), and when the compiler uses them for you.
Memory
Where data lives, how long it takes to reach, and what the hardware does to hide the wait.
- 08 The memory hierarchy
Registers, caches, RAM and storage, and the large gaps in speed between each level.
- 09 CPU caches and coherence
Cache lines, associativity, how cores keep their caches in agreement (MESI), and false sharing.
Try it: CPU cache simulator - 10 Virtual memory and the TLB
How every address goes through page tables, how the TLB keeps that fast, and when huge pages help.
Try it: Virtual memory simulator - 11 NUMA and memory bandwidth
Why memory attached to another socket is slower to reach, and how Linux decides where memory and threads go.
Devices
How data gets between the CPU, drives, network cards and GPUs.
- 12 PCIe, DMA and interrupts
How network cards and drives copy data straight into memory, and how they tell the CPU it has arrived.
- 13 SSDs and the flash translation layer
Why flash is written in small pages but erased in large blocks, what the drive’s firmware does about it, and NVMe queues.
- 14 GPUs and accelerators
Thousands of simple cores running the same code on different data, high-bandwidth memory, and chips built for machine learning.
Start-up
What happens between pressing the power button and the kernel taking over.
- 15 From power-on to the kernel
Reset, firmware (UEFI), the bootloader and the kernel, plus microcode updates, Secure Boot and the TPM.
Where the figures come from
Cycle counts, cache sizes and latencies in these chapters come from vendor manuals and specifications where they exist, Agner Fog’s instruction tables, and independent measurements published by Chips and Cheese. Textbook explanations follow Patterson and Hennessy, and Bryant and O’Hallaron.